4,194,304 words x 4 bit cmos dynamic ram description the gm71v(s)16403c/cl is the new generation dynamic ram organized 4,194,304 words x 4 bit. gm71v(s)16403c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71v(s)16403c/cl offers extended data out (edo) page mode as a high speed access mode. multiplexed address inputs permit the gm71v(s)16403c/cl to be packaged in a standard 300 mil 24(26) pin soj, and a standard 300 mil 24(26) pin plastic tsop ii. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. system oriented features include single power supply 3.3v +/- 0.3v tolerance, direct interfacing capability with high performance logic families such as schottky ttl. features * 4,194,304 words x 4 bit organization * extended data out mode capability * single power supply (3.3v +/- 0.3v) * fast access time & cycle time * low power active : 324/288/252mw (max) standby : 7.2mw (cmos level : max) : 0.36 mw (l-version : max) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 4096 refresh cycles/64ms * 4096 refresh cycles/128ms (l-version) * self refresh operation (l-version) * battery backup operation (l-version) * test function : 16bit parallel test mode ( unit: ns) gm71v(s)16403c/cl-5 gm71v(s)16403c/cl-6 gm71v(s)16403c/cl-7 t rac t cac t rc t hpc 50 60 13 15 84 104 20 25 70 18 124 30 pin configuration ( top view) 24(26) soj v cc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 v cc v ss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 24(26) tsop ii v cc i/o1 i/o2 we ras a11 a10 a0 a1 a2 a3 v cc v ss i/o4 i/o3 cas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 GM71V16403C gm71vs16403cl rev0.1/apr ? 01
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 pin description pin function pin function a0-a11 a0-a11 i/o1-i/o4 v cc v ss address inputs refresh address inputs data input/data output row address strobe column address strobe read/write enable output enable power (+3.3v) ground ordering information type no. access time package gm71v(s)16403cj/clj-5 gm71v(s)16403cj/clj-6 gm71v(s)16403cj/clj-7 50 ns 60ns 70ns 300 mil 24(26) pin plastic soj gm71v(s)16403ct/clt-5 gm71v(s)16403ct/clt-6 gm71v(s)16403ct/clt-7 50 ns 60ns 70ns 300 mil 24(26) pin plastic tsop ii absolute maximum ratings symbol parameter rating unit t a t stg v in/out v cc i out 0 ~ 70 -55 ~ 125 -0.5 ~ vcc +0.5 (<=4.6v(max)) -0.5 ~ 4.6 50 ambient temperature under bias storage temperature voltage on any pin relative to v ss supply voltage relative to v ss short circuit output current v v ma p d 1.0 power dissipation w note: all voltage referred to vss . ras cas recommended dc operating conditions (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 3.6 v cc + 0.3 0.8 typ 3.3 - - min 3.0 2.0 -0.3 c c nc no connection oe we
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 dc electrical characteristics (v cc = 3.3v+/-0.3v, v ss = 0v, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2 ma ) unit max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2 ma ) i cc1 operating current average power supply operating current (ras, cas cycling : t rc = t rc min) i cc2 standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) i cc3 ras only refresh current average power supply current ras only refresh mode ( t rc = t rc min) i cc4 i cc5 standby current (cmos) power supply standby current (ras, cas >= v cc - 0.2v, d out = high-z) 1 - i cc6 cas-before-ras refresh current ( t rc = t rc min) i cc7 100 - i cc8 i l(i) 10 -10 i l(o) 10 -10 input leakage current any input (0v <= v in <= 4.6v) output leakage current (d out is disabled, 0v <= v out <= 4. 6v) i cc9 self-refresh mode current (ras, cas<=0.2v , d out = high-z, cmos interface) 200 - - standby current ras = v ih cas = v il d out = enable 5 1 ma edo page mode current average power supply current edo page mode ( t hpc = t hpc min) note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. cas = l (<=0.2) while ras = l (<=0.2). 5. l-version. 90 - 50 ns 60 ns 70 ns 80 70 - 2 - - 90 - 50 ns 60 ns 70 ns 80 70 - - - 80 - 50 ns 60 ns 70 ns 70 65 - v v ma ua ua ua ua 5 5 ma 1, 2 ma ma 2 ma 1, 3 ma - 90 - 50 ns 60 ns 70 ns 80 70 - battery backup operating current(standby with cbr refresh) (cbr refresh, t rc = 31.3us , t ras <= 0.3 us, d out = high-z, cmos interface) 300 ua - 4,5
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 capacitance (v cc = 3.3v +/- 0.3v, t a = 25c) ac characteristics (v cc = 3.3v +/- 0.3v, v ss = 0v, t a = 0 ~ 70c, notes 1, 2, 18) read, write, read-modify-write and refresh cycles (common parameters) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit nf nf pf max 5 7 7 min - - - test conditions input rise and fall times : 2ns input levels: v il = 0v, v ih =3v input timing reference levels : 0.8v, 2.0v output timing reference levels : 0.8v, 2.0v output load : 1 ttl gate + c l (100pf) (including scope and jig) note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable d out . symbol parameter note max unit min max min max min t rc random read or write cycle time 84 - 104 - 124 - t rp ras precharge time 30 - 40 - 50 - t ras ras pulse width 50 10,000 60 10,000 70 10,000 t cas cas pulse width 8 10,000 10,000 10,000 10 13 t asr row address set up time 0 - - - 0 0 t rah row address hold time 8 - - - 10 10 t asc column address set-up time 0 - - - 0 0 t cah column address hold time 8 - - - 10 13 t rcd ras to cas delay time 12 37 45 52 14 14 3 t rad ras to column address delay time 10 25 30 35 12 12 4 t rsh ras hold time 10 - - - 13 13 t csh cas hold time 35 - - - 40 45 t crp cas to ras precharge time 5 - - - 5 5 t t transition time (rise and fall) 2 50 50 50 2 2 7 t dzo oe delay time from d in 0 - - - 0 0 t dzc cas delay time from d in 0 - - - 0 0 gm71v(s)16403 c/cl-5 oe to d in delay time 13 - - - 15 18 5 6 6 t cp cas precharge time 8 - 10 - 13 - t odd gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 read cycle symbol parameter unit max note min max min t rac access time from ras - 60 - 70 ns t cac access time from cas - 15 - 18 ns t aa access time from address - 30 - 35 ns t rcs read command setup time 0 - 0 - ns t rch read command hold time to cas 0 - - ns 0 t rrh read command hold time to ras 5 - - ns 5 t ral column address to ras lead time 30 - - ns 35 12 12 t clz cas to output in low-z 0 - - ns 0 8.9.19 9,10, 17,19 9,11, 17,19 t cal column address to cas lead time 18 - - ns 23 t off output buffer turn-off time - 15 15 ns - 13 t oac access time from oe - 15 - 18 ns 9 t oh output data hold time 3 - - ns 3 t oho output data hold time from oe 3 - - ns 3 t oez output buffer turn-off time to oe - 15 15 ns - 13 t cdd cas to d in delay time 15 - - ns 18 5 t wdd we to d in delay time 15 - - ns 18 t ohr output data hold time from ras 3 - - ns 3 t ofr output buffer turn-off time to ras - 15 15 ns - t wez output buffer turn-off to we - 15 15 ns - t rdd ras to d in delay time 15 - - ns 18 t rchr read command hold time from ras 60 - - ns 70 gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 max min - 50 - 13 - 25 0 - 0 - 5 - 25 - 0 - 15 - - 13 - 13 3 - 3 - - 13 13 - 13 - 3 - - 13 - 13 13 - 50 - gm71v(s)16403 c/cl-5
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 read- modify-write cycle refresh cycle write cycle symbol parameter note max unit min max min 0 - 0 - 10 - 13 - 10 - 10 - write command to ras lead time 10 - 13 - write command to cas lead time 10 - - 13 0 - - 0 10 - - 13 15 15 write command setup time write command hold time write command pulse width data-in setup time data-in hold time 14 gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 ns min 0 - 8 - 8 - - - 0 - - max gm71v(s)16403 c/cl-5 8 8 8 ns ns ns ns ns ns symbol parameter note max unit min max min 136 - 161 - 79 - 92 - 34 - 40 - 49 - 57 - 14 14 14 15 - 18 - read-modify-write cycle time ras to we delay time cas to we delay time column address to we delay time oe hold time from we gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 ns ns ns ns ns min 111 - 67 - 30 - 42 - 13 - max gm71v(s)16403 c/cl-5 symbol parameter note max unit min max min 5 - 5 - ns 10 - 10 - ns 5 - 5 - ns gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 0 - 0 - ns t wcs t wch t wp t rwl t cwl t ds t d h t rwc t rwd t cwd t awd t oeh t csr t chr t rpc t wrp t wrh 10 - 10 - ns cas setup time (cas-before-ras refresh cycle) cas hold time (cas-before-ras refresh cycle) ras precharge to cas hold time we setup time (cas-before-ras refresh cycle) we hold time (cas-before-ras refresh cycle) min 5 - 8 - 5 - gm71v(s)16403 c/cl-5 0 - 10 - max
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 refresh symbol parameter unit max min max min t ref - 64 - test mode cycle edo page mode read-modify-write cycle edo page mode cycle * 18 t ref refresh period refresh period (l - version) - 128 - gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 ms ms 64 128 symbol parameter max unit min max min t hpc 25 - 30 - t rasp t acp 35 - 40 - t rhcp - - 100,000 100,000 - - 35 40 gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 t doh t col t cop t rchp 3 3 - - - - 10 13 5 5 35 40 ns ns ns ns ns ns ns ns min 20 - 30 - - - gm71v(s)16403 c/cl-5 3 - - - - 5 30 max 100,000 8 edo page mode ras pulse width access time from cas precharge ras hold time from cas precharge edo page mode cycle time read command hold time from cas precharge cas hold time referred oe output data hold time from cas low cas to oe setup time symbol parameter max unit min max min t hprwc 68 - 79 - ns t cpw 54 - 62 - ns edo page mode read-modify-write cycle time we delay time from cas precharge gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 max min 57 - 45 - gm71v(s)16403 c/cl-5 symbol parameter unit max note 4096 cycles 4096 cycles note 9,17,19 16 20 9 note 14 note min max min t wts 0 - 0 - ns t wth 10 - 10 - ns test mode we setup time test mode we hold time gm71v(s)16403 c/cl-6 gm71v(s)16403 c/cl-7 max min 0 - 10 - gm71v(s)16403 c/cl-5 max min - 64 - 128 gm71v(s)16403 c/cl-5 30
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 notes: ac measurements assume t t = 2ns. an initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras-only refresh or cas-before- ras refresh). if the internal refresh counter is used, a minimum of eight cas-before-ras refresh cycles are required. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . either t odd or t cdd must be satisfied. either t dzo or t dzc must be satisfied. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). assume that t rcd <= t rcd (max) and t rad <= t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 1 ttl loads and 100pf. assume that t rcd >= t rcd (max) and t rcd + t cac (max) >= t rad + t aa (max). assume that t rad >= t rad (max) and t rcd + t cac (max) <= t rad + t aa (max). either t rch or t rrh must be satisfied for a read cycles. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. self refresh mode ( l-version ) symbol parameter note max unit min max min gm71vs16403 cl-6 gm71vs16403 cl-7 t rass 100 - 100 - m s t rps 110 - 130 - ns ras pulse width ( self-refresh ) t chs -50 - -50 - ns ras precharge time ( self-refresh ) cas hold time ( self-refresh ) min 100 - 90 - -50 - max gm71vs16403 cl-5
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs >= t wcs (min), the cycles is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd >= t rwd (min), the t cwd >= t cwd (min), and t awd >= t awd (min), or t cwd >= t cwd (min), t awd >= t awd (min) and t cpw >= t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. these parameters are referenced to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. t rasp defines ras pulse width in edo page mode cycles. access time is determined by the longest among t aa or t cac or t acp . the 16m dram offers a 16-bit time saving parallel test mode. address ca0 and ca1 for the 4m x 4 are don't care during test mode. test mode is set by performing a we-and-cas-before- ras (wcbr) cycle. in 16-bit parallel test mode, data is written into 4 bits in parallel at each i/o (i/o1 to i/o4) and read out from each i/o. if 4 bits of each i/o are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. if they are not equal, data output pin is a low state, then the device has failed. refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. to get out of test mode and enter a normal operation mode, perform either a regular cas-before-ras refresh cycle or ras-only refresh cycle. in a test mode read cycle, the value of t rac , t aa , t cac and t acp is delayed by 2ns to 5ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle(edo page mode mix cycle (1),(2)), minimum value of cas cycle ( t cas + t cp + 2t t ) becomes greater than the specified t hpc (min) value. the value of cas cycle time of mixed edo page mode is shown in edo page mode mix cycle (1) and (2). 18. 19. 20. 14. 15. 16. 17.
GM71V16403C gm71vs16403cl rev0.1/apr ? 01 package dimension unit: inches (mm) 24(26) tsop (type ii) 24(26) soj 0.669(17.00) max 0.661(16.80) min 0.295(7.49) min 0.329(8.38) min 0.340(8.64) max 0.147(3.75) max 0.128(3.25) min 0.020(0.50) max 0.015(0.38) min typ 0.050(1.27) 0.305(7.75) max 0.260(6.60) min 0.275(6.99) max 0.025(0.64) min 0.032(0.81) max 0.026(0.66) min 0.085(2.16) min 0.020(0.50) max 0.012(0.30) min typ 0.050(1.27) 0.007(0.18) max 0.003(0.08) min 0.047(1.20) max 0.041(1.05) max 0.037(0.95) min 0.296(7.52) min 0.303(7.72) max 0.678(17.24) max 0.670(17.04) min 0.355(9.02) min 0.371(9.42) max 0.024(0.60) max 0.016(0.40) min 0.008(0.21) max 0.004(0.12) min 0 ~ 5 ?
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